The present invention relates generally to improvements in very long instruction word (VLIW) processing, and more particularly to methods and apparatus for providing port priority functions in a VLIW processor.
In VLIW processors, multiple short instruction words (SIWs) are typically executed in parallel to provide high performance. It is possible to have multiple instructions within a VLIW simultaneously target the same register within a register file. This simultaneous targeting produces a conflict situation. One of the ways hardware typically deals with the situation is by treating the conflicting instructions as a no-operation (nop) and indicating an error has occurred, or by indicating an error situation exists and assigning priorities to the instructions to control which single instruction wins in writing to the conflicting target register. When the conflict xe2x80x9chazardxe2x80x9d occurs, it usually means an error situation has occurred and typically no advantage can be found in the situation.
In the present invention, write port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a ManArray reconfigurable register file, as further described in U.S. patent application Ser. No. 09/169,255 entitled xe2x80x9cMethods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File with Extended Precisionxe2x80x9d filed Oct. 9, 1998, it is possible to have instructions that operate on double-word data (64-bits) mixed with instructions that operate on single-word data (32-bits) within the same VLIW. By resolving a write priority conflict on a word basis, it is possible to have half of a double-word operation complete, on the single word portion of the CRF that was not in conflict, while the other conflicting word operation follows the dictates of a hardware priority mechanism. It is also possible to have instructions that operate on double-word data (64-bits) or word data (32-bits) mixed in a VLIW with instructions that operate on half-word data (16-bits), such as a half-word load instruction. In the 64-bit and 16-bit mixed operation case, by resolving a write priority conflict on a half-word basis, it is possible to have the three half-word portions (48-bits) of a double-word operation (64-bits) complete, on the three half-word portions of the CRF register that are not in conflict, while the other conflicting single half-word operation (16-bits) follow the dictates of a hardware priority mechanism. In a similar manner, byte write priorities only come into affect on the byte portions of targeted registers that are in conflict. If no conflict exists, the operation completes normally. This capability allows unique functions that have not typically been available, on prior art processors, as described further below.